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Cours Architecture des Ordinateurs Programmation Assembleur Jean-Claude Bajard IUT - universit´e Montpellier 2 Assembleur Pentium Pr´ esentation du Pentium Premi`ere ann´ee 2003 2 Assembleur The table below shows the dramatic increases in performance and transistor count of the IA processors over their history, as predicted by Moore’s Law, and also summarizes the evolution of other key features of the architecture. Pentium Table 2-1. Processor Performance Over Time and Other Intel Architecture Key Features Date of Product Introduction Perform -ance in MIPs1 Max. CPU Frequency at Introduction 8086 1978 0.8 8 MHz Intel 286 1982 2.7 Intel386™ DX 1985 Intel486™ DX No.
Of Transis -tors on the Die Main CPU Register Size2 Extern. Data Bus Size2 Max. Space Caches in CPU Package3 29 K 16 16 1 MB None 12.5 MHz 134 K 16 16 16 MB Note 3 6.0 20 MHz 275 K 32 32 4 GB Note 3 1989 20 25 MHz 1.2 M 32 32 4 GB 8KB L1 Pentium® 1993 100 60 MHz 3.1 M 32 64 4 GB 16KB L1 Pentium® Pro 1995 440 200 MHz 5.5 M 32 64 64 GB 16KB L1; 256KB or 512KB L2 Pentium II® 1997 466 266 7M 32 64 64 GB 32KB L1; 256KB or 512KB L2 Pentium® III 1999 1000 500 8.2 M 32 GP 128 SIMD-FP 64 64 GB 32KB L1; 512KB L2 Intel Processor NOTES: 1. Performance here is indicated by Dhrystone MIPs (Millions of Instructions per Second) because even 2003though MIPs are no longer considered a preferred measure of CPU performance, they are the only benchmarks that span all six generations of the IA. The MIPs and frequency values given here correspond to the maximum CPU frequency available at product introduction. Premi`ere ann´ee 2. Main CPU register size and external data bus size are given in bits.
Note also that there are 8 and 16-bit 3 Assembleur Pentium Architectural Features Figure 2-1. Embedded Pentium® Processor Block Diagram Control DP Logic4 Branch Prefetch Target Buffer Address TLB Code Cache 16 Kbytes1 1283 Prefetch Buffers Instruction Pointer 64-Bit Data Bus Bus Unit Control ROM Instruction Decode Branch Verification and Target Address Control Unit Page Unit V-Pipeline Connection U-Pipeline Connection Floating Point Unit Address Address Generate Generate (U Pipeline) (V Pipeline) MMX™ Technology Unit2 32-Bit Address Bus Control Integer Register File 64-Bit 64 Data Bus ALU (U Pipeline) 32 32-Bit Addr. Bus ALU (V Pipeline) Control Register File Add Divide Barrel Shifter 80 Multiply 80 Data APIC5 Control 32 32 32 Data Cache 16 Kbytes1 32 TLB 32 32 A6105-01 NOTES: 1. The Code and Data caches are each 8 Kbytes in size on the embedded Pentium® processor (at 100/133/166 MHz). The MMX Technology Unit is present only on the embedded Pentium processor with MMX™ technology.
The internal instruction bus is 256 bits wide on the embedded Pentium processor. Dual processing is not present on the embedded Pentium processor with Voltage Reduction Technology or the low-power embedded Pentium processor with MMX technology. The APIC is not present on the embedded Pentium proces sor with Voltage Reduction Technology. Premi`ere ann´ee 2003 The dual processor configuration allows two embedded Pentium processors to share a single L2 cache for a low-cost symmetric multi-processor system. The two processors appear to the system as a single embedded Pentium processor. Multiprocessor operating systems properly schedule 4.
Memory pointers Although all of these registers are available for general storage of operands, results, and pointers, caution should be used when referencing the ESP register. The ESP register holds the stack pointer and as a general rule should not be used for any other purpose. Assembleur 31 General-Purpose Registers Pentium 0 EAX EBX ECX EDX ESI EDI EBP ESP Segment Registers 0 15 CS DS SS ES FS GS 31 Status and Control Registers 0 EFLAGS 31 0 EIP Figure 3-3. Application Programming Registers Many instructions assign specific registers to hold operands. For example, string instructions use the contents of the ECX, ESI, and EDI registers as operands.
When using a segmented 2003 memory model, some instructions assume that pointers in certain registers are relative to Premi`ere ann´ee 5 Programmation Assembleur format ATT- GNU Assembleur Format d’une instruction assembleur (gnu ATT) ´ etiquette: mn´ emonique op´ erandes Pentium #commentaires. ´ etiquette: adresse effective de l’instruction, utile pour les branchements. mn´ emonique nom g´en´erique donn´e ` a une instruction: ADD, JUMP. op´ erandes arguments de l’instruction: 0, 1 ou 2. #commentaires non pris en compte au moment de l’assemblage Premi`ere ann´ee 2003 7 Assembleur Type des op´ erandes op´erande 1: source registre Premi`ere ann´ee 2003 Pentium op´erande 2: destination registre imm´ediat registre m´emoire registre registre m´emoire imm´ediat m´emoire 8 register set found in the 8086 and Intel 286 processors and can be referenced with the names AX, BX, CX, DX, BP, SP, SI, and DI. Each of the lower two bytes of the EAX, EBX, ECX, and Assembleur Pentium EDX registers can be referenced by the names AH, BH, CH, and DH (high bytes) and AL, BL, CL, and DL (low bytes). 31 General-Purpose Registers 8 7 16 15 16-bit 32-bit AL AX EAX BH BL BX EBX CH CL CX ECX DH DL DX EDX 0 AH BP EBP SI ESI DI EDI SP ESP Figure 3-4.
Alternate General-Purpose Register Names 3.6.2. Segment Registers The segment registers (CS, DS, SS, ES, FS, and GS) hold 16-bit segment selectors. A segment selector is a special pointer that identifies a segment in memory. To access a particular segment Premi`ere ann´ee 2003 9 Assembleur Les modes d’adressages de la m´ emoire Pentium. absolu = 0x8049514. registre indirecte: ∗ base = (%eax) ∗ base + d´eplacement= 4(%eax) ∗ base + index. pas + d´eplacement = dep(base,index,scale) =4(%eax,%ebx,2) Premi`ere ann´ee 2003 10.
Scale factor—A value of 2, 4, or 8 that is multiplied by the index value. The offset which results from adding these components is called an effective address. Pentium Each of modes either a positived’adressages or negative (2s complement) value, with the excepthese components can haveLes tion of the scaling factor. Figure 5-6 shows all the possible ways that these components can be combined to create an effective address in the selected segment. Assembleur Base Index EAX EBX ECX EDX ESP EBP ESI EDI EAX EBX ECX EDX EBP ESI EDI +. Scale Displacement 1 None 2 8-bit + 3 16-bit 4 32-bit Offset = Base + (Index ∗ Scale) + Displacement Figure 5-6. Offset (or Effective Address) Computation The uses of general-purpose registers as base or index components are restricted in the following manner:.
The ESP register cannot be used as an index register. Premi`ere ann´ee 2003. When the ESP or EBP register is used as the base, the SS segment is the default segment.11 In all other cases, the DS segment is the default segment. Assembleur Types des instructions Pentium. Transfert: mouvement de donn´ees, MOV. Arithm´etique et logique: ADD, AND. Contrˆ ole: ∗ saut conditionnel ∗ appel de proc´edure.
Interruption: en g´en´eral: int num´ero de 0 ` a 255 Premi`ere ann´ee 2003 12 All Intel Architecture instruction encodings are subsets of the general instruction format shown in Figure 2-1. Instructions consist of optional instruction prefixes (in any order), one or two Assembleurprimary opcode bytes, an addressing-form specifier (if required) consisting of the ModR/M byte (Scale-Index-Base) byte, a displacement (if required), and an immediate and sometimes the SIB Format d’une instruction machine data field (if required). Pentium Instruction Prefixes Opcode ModR/M SIB Displacement Immediate Up to four prefixes of 1-byte each (optional) 1 or 2 byte opcode 1 byte (if required) 1 byte (if required) Address displacement of 1, 2, or 4 bytes or none Immediate data of 1, 2, or 4 bytes or none 32 7 3 2 7 65 Mod Reg/ Opcode 0 R/M 6 5 Scale Index 0 Base Figure 2-1.
Intel Architecture Instruction Format 2.2. INSTRUCTION PREFIXES. longueur d’une instruction de un `a 16 octets The instruction prefixes are divided into four groups, each with a set of allowable prefix codes:. Lock and repeat prefixes.
— F0H—LOCK prefix. — F2H—REPNE/REPNZ prefix (used only with string instructions). Premi`ere ann´ee —2003F3H—REP prefix (used only with string instructions). — F3H—REPE/REPZ prefix (used only with string instructions).
13 Assembleur Structure d’un programme: les segments Pentium. A l’origine un programme comportait au moins trois segments associ´es `a des registres (16 bits): ∗ code: CS EIP =.text ∗ donn´ees: DS =.data ∗ pile: SS ESP=.bss. La gestion de la m´emoire est fortement li´ee au syst`eme d’exploitation. Elle peut ˆetre de deux types: segment´ee (8086 avec msdos) ou pagin´ee (linux), l’utilisation des regitres ”segment” pour l’adressage physique d´epend de cette gestion (voir doc Pentium Premi`ere ann´ee 2003 14 Assembleur Structure d’un programme: Pentium.data bonjour:.string 'hello world! N' taille:.long.
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